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* Standard Software Driver (SSD) for C55 Flash module v1.1.0.
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#include "fnet.h"

#if FNET_MPC && FNET_CFG_CPU_MPC5744P && FNET_CFG_COMP_GHS

/*For writing SPR*/
#define mtspr(rn, v)    __asm__ volatile("mtspr " #rn ",%0" : : "r" (v))

/*For reading SPR*/
#define mfspr(reg, spr)    __asm__ volatile("mfspr %0, " # spr : "=r"  (reg))

#define E200CORE_SYNC()                __asm__("msync")        /* Memory synchronize  */
#define E200CORE_ISYNC()               __asm__("se_isync" )    /* Instruction synchronize */
#define E200CORE_SPR_GET(lhs, reg)     mfspr( lhs, reg)        /* read from special register*/
#define E200CORE_SPR_SET(reg, val)     mtspr( reg, val)        /* write to special register*/
#define E200CORE_L1CSR0                1010                    /* L1 Cache Control and Status Register 0 */
#define E200CORE_L1CSR0_CE             0x00000001              /* Data cache enable */
#define E200CORE_L1CSR0_CWM            0x00100000              /* Data cache Write mode */

/*FUNCTION*-------------------------------------------------------------------
*
* Function Name    : dcache_enable
* Returned Value   : none
* Comments         :
*   This function enables the data cache
*
*END*----------------------------------------------------------------------*/

void fnet_mpc5744p_dcache_enable(
    void
)  /* Body */
{
    register fnet_uint32_t i;
    /* Read L1CSR0 */
    E200CORE_SPR_GET(i, E200CORE_L1CSR0);
    /* enable copy-back mode,enable cache */
    i |= E200CORE_L1CSR0_CE | E200CORE_L1CSR0_CWM;
    /* Memory Synchronize */
    E200CORE_SYNC();
    /* Instruction Synchronize */
    E200CORE_ISYNC();
    /* Write to L1CSR0 */
    E200CORE_SPR_SET(E200CORE_L1CSR0, i);
    /* Instruction Synchronize */
    E200CORE_ISYNC();
} /* Endbody */

/*FUNCTION*-------------------------------------------------------------------
*
* Function Name    : dcache_disable
* Returned Value   : none
* Comments         :
*   This function disables the data cache (if possible)
*
*END*----------------------------------------------------------------------*/

void fnet_mpc5744p_dcache_disable(
    void
)  /* Body */
{
    register fnet_uint32_t val;

    E200CORE_SPR_GET(val, E200CORE_L1CSR0); /* L1CSR0 */
    val &= ~E200CORE_L1CSR0_CE;
    /* Memory Synchronize */
    E200CORE_SYNC();
    /* Instruction Synchronize */
    E200CORE_ISYNC();
    E200CORE_SPR_SET(E200CORE_L1CSR0, val);
    /* Instruction Synchronize */
    E200CORE_ISYNC();
} /* Endbody */

#endif
